The IBM-SP2 operated at the University of Michigan is a collection of 32 Power-2 chips processors grouped into a number of frames [IBM94]. Each Power-2 chip processor has 256 MBytes of memory. The group of processors has an additional high performance switch (HP-2). The high performance switch can be linked in either statically (when the parallel program is compiled) or dynamically (when the program is invoked). The IBM-SP2 has a latency of 40 micro seconds and bandwidth of 40 MBytes/sec. The IBM Message Passing Library (MPL) routines were used to run the parallel tasks.