Big Data Benchmarking

SDSC keeps close tabs on the latest advances in compute hardware, memory, storage, and networking, along with the latest techniques to manage data and computation. We benchmark systems to look deeply into how they work, where they run into bottlenecks, and how to improve their performance.

Benchmarking of array operations on Intel’s Xeon Phi show the impact of cache and memory latency (the stair steps) and the processor’s prefetcher (zig-zag lines under the stair steps).

Benchmarking of array operations on Intel’s Xeon Phi show the impact of cache and memory latency (the stair steps) and the processor’s prefetcher (zig-zag lines under the stair steps).

To explore a service engagement or request further information, please visit our Industry Partners Program webpage or contact us at ipp@sdsc.edu.