SDSC Receives Revolutionary Tera MTA Multiprocessor Supercomputer

Published 04/28/1998

For more information, contact:
Ann Redelfs, SDSC, 619-534-5032 (voice), 619-534-5113 (FAX), redelfs@sdsc.edu

UNIVERSITY OF CALIFORNIA, SAN DIEGO -- The San Diego Supercomputer Center (SDSC) has accepted delivery of a two-processor Multithreaded Architecture (MTA) computer system built by Tera Computer Company of Seattle, Washington.

"We've been pleased to have early access to the one-processor MTA system since December, and have achieved some encouraging results," said Wayne Pfeiffer, deputy director at SDSC and principal investigator for the MTA evaluation projects. "We look forward to working with larger MTA systems, and the opportunity to verify performance on real-world applications."

SDSC's Tera MTA system will be upgraded to larger configurations in stages, with delivery of production circuit boards and other components. A major anticipated advantage of the MTA over other supercomputers is its unique degree of scalability -- its application performance increases in proportion to the number of processors, with no change in the programming model. The MTA is designed to provide high performance, broad applicability and ease of programming in a single system, and uses a unique architecture in which each processor can support up to 128 threads of execution, which allows more efficient processor and memory use than traditional architectures.

"Our Multithreaded Architecture is a radical departure from that of conventional supercomputers," said Burton Smith, Tera's chairman, co-founder, and chief architect of the MTA. "It overcomes the scalability and programmability hurdles faced by other approaches to high-performance parallel computing."

Delivery of the computer to SDSC results from the National Science Foundation's multi-year award of $4.2 million to the University of California, San Diego (UCSD) to fund the acquisition and evaluation of the Tera MTA system. The machine will be used for a wide variety of applications, including molecular modeling, aircraft design, database management, and visualization. UCSD also has received a $1.9 million, 18-month award from the Defense Advanced Research Projects Agency (DARPA) to to evaluate multithreading for defense applications. SDSC's partners in the DARPA research project include the California Institute of Technology (Caltech),NASA Jet Propulsion Laboratory (JPL), The Boeing Company, and Sanders (a Lockheed Martin Company).

"The upgraded MTA is up and running in our machine room, and it's passed its hardware diagnostics," said Pfeiffer. "Over the coming months we'll be putting the machine through its paces and verifying its performance with some real-world benchmarks." UCSD computer scientist Larry Carter and SDSC/UCSD researcher Allan Snavely will run a standard suite of software benchmarks developed by NASA on the upgraded system. SDSC expects to announce the results of the benchmark tests in the near future.

SDSC expects to make the Tera MTA available to a limited number of additional scientists at UCSD and other institutions sometime later this year. "We have a lot of researchers who are eager to run compute-intensive programs on this machine," Pfeiffer said. "Once our tests are further along, we plan to make the MTA available to the scientific research community through the National Partnership for Advanced Computational Infrastructure."

"This important milestone begins a new chapter for Tera," said Jim Rottsolk, Tera's president, chief executive officer, and co-founder. "Our challenge now is to deliver larger systems on a consistent basis. We look forward to working with SDSC in expanding our system in San Diego and with other potential customers who are monitoring the SDSC evaluation."

A single-processor prototype MTA already has broken the speed record for the NAS Parallel Integer Sort benchmark. The results of more recent benchmark tests run on a single-processor MTA system were announced this past November at SC97, the annual supercomputing conference, and are available on the Web at http://www.cs.ucsd.edu/users/carter/Tera/tera.html.

Digitized photographs of the Tera MTA's installation at SDSC are available on the Web at http://www.sdsc.edu/~allans/2-processor-install/pictures.html (JPEG images, 640x480 pixels).

Tera Computer Company designs, builds, and sells high-performance general-purpose parallel computer systems. For more information about Tera and its MTA systems, contact the company at 2815 Eastlake Avenue E., Seattle, WA 98102. Phone: (206) 490-2000. Fax: (206) 325-2433. E-mail: info@tera.com, or http://www.tera.com.

SDSC is a research unit of the University of California, San Diego, and is sponsored by the National Science Foundation through the National Partnership for Advanced Computational Infrastructure and by other federal agencies, the State and University of California and private organizations. For additional information about SDSC, see http://www.sdsc.edu/ and http://www.npaci.edu/.